NVIDIA is considering adjustments to some designs of its AI platform, Feynman, scheduled for release in 2028, to align with manufacturing constraints. There are analyses suggesting that the performance competition among AI accelerators is directly linked to advanced processes, packaging, and high-bandwidth memory (HBM) supply capabilities. According to CryptoBriefing, NVIDIA is exploring the possibility of modifying certain configurations of the Feynman platform to circumvent production limitations of TSMC's A16 process. Feynman is introduced as utilizing TSMC's A16 process, 3D die stacking, rear power delivery, and custom HBM. CEO Jensen Huang first unveiled the Feynman architecture at GTC 2025 and presented additional technical details at GTC 2026 this March. The TSMC A16 is an advanced process at 1.6 nanometers, intended for the production of AI accelerators and high-performance computing (HPC) chips. As of March 2026, A16 wafer production capacity is booked until 2028, with TSMC planning to ramp up A16 production to about 20,000 wafers per month by the end of 2027. NVIDIA is testing low-capacity memory configurations for the Rubin Ultra Accelerator, stating that these optimizations enable the deployment of more GPUs and AI systems. Currently, the final product specifications or supply schedule changes for Feynman have not been confirmed.
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