Intel Unveils EMIB-T Supporting 120mm Packages, Challenging TSMC

Intel has unveiled its next-generation advanced packaging technology, EMIB-T, which supports packages up to 120×120mm. While the technology validation yield has reached 90%, it should be distinguished from the final mass production yield. EMIB-T improves power delivery and high-speed signal transmission performance by utilizing Through-Silicon Vias (TSV), with goals of a 25-micrometer bump pitch, 120×120mm package, integration of computation and memory silicon across more than nine reticle areas, and support for HBM4e at 12Gb/s and UCIe at 64Gb/s. The increasing size of AI accelerators and high-performance computing (HPC) chips has brought attention to EMIB-T. TSMC's CoWoS connects logic chips and HBM using large silicon interposers, while Intel's EMIB series employs a structure that places smaller silicon bridges, reducing silicon usage and manufacturing burden. Analyst Guo Mingqi noted that while reaching a 90% technology validation yield for EMIB-T is positive, raising the yield from 90% to over 98% will be challenging. TSMC is expanding the production scale of CoWoS and plans to produce 14 times the reticle products by 2026. Intel is expanding its advanced packaging business for external customers, stating that the contract scale is approaching several billion dollars annually. The competitiveness of EMIB-T will be evaluated after the mass production yield and actual adoption cases of external customer products are disclosed.

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